CVE-2020-24512

Published: 8 June 2021

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

From the Ubuntu security team

Travis Downs discovered that some Intel processors did not properly flush cache-lines for trivial-data values. This may allow an unauthorized user to infer the presence of these trivial-data-cache-lines via timing sidechannel attacks. A local attacker could use this to expose sensitive information.

Notes

INTEL-TA-00464
no kernel component to this MCU update

Priority

Medium

CVSS 3 base score: 2.8

Status

References

• https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-24512
• https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00464.html
• https://ubuntu.com/security/notices/USN-4985-1
• NVD
• Launchpad
• Debian