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CVE-2020-24512

Published: 8 June 2021

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

From the Ubuntu Security Team

Travis Downs discovered that some Intel processors did not properly flush cache-lines for trivial-data values. This may allow an unauthorized user to infer the presence of these trivial-data-cache-lines via timing sidechannel attacks. A local attacker could use this to expose sensitive information.

Notes

AuthorNote
sbeattie
INTEL-TA-00464
no kernel component to this MCU update

Priority

Medium

Cvss 3 Severity Score

2.8

Score breakdown

Status

Package Release Status
intel-microcode
Launchpad, Ubuntu, Debian
bionic
Released (3.20210608.0ubuntu0.18.04.1)
focal
Released (3.20210608.0ubuntu0.20.04.1)
groovy
Released (3.20210608.0ubuntu0.20.10.1)
hirsute
Released (3.20210608.0ubuntu0.21.04.1)
impish
Released (3.20210608.0ubuntu1)
jammy
Released (3.20210608.0ubuntu1)
precise Does not exist

trusty
Released (3.20210608.0ubuntu0.14.04.1+esm1)
upstream Needs triage

xenial
Released (3.20210608.0ubuntu0.16.04.1+esm1)

Severity score breakdown

Parameter Value
Base score 2.8
Attack vector Local
Attack complexity High
Privileges required Low
User interaction None
Scope Changed
Confidentiality Low
Integrity impact None
Availability impact None
Vector CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:L/I:N/A:N